1. Field of the Invention
The present invention relates to a direct memory access device and, more specifically, to a direct memory access device which controls a data transfer mode.
2. Description of the Related Art
FIG. 13 shows a direct memory access method according to a prior art. In direct memory access (DMA), data are transferred between an input/output device and a memory or between memories. A clock CK is a synchronous clock for DMA. As for an address AD, for example, locations 0 through 99 are data transfer source addresses and locations 100 through 199 are data transfer destination addresses. In the locations 1 to 3, data D0 to D2 are stored respectively. The data D0 to D2 are 1 byte each, and thus 3 bytes in total. A data bus DT is 1 word (16 bits) wide. As for the data bus DT, 0 to 7 bits are a first byte and 8 to 15 bits are a second byte. A pulse of a read signal RD indicates a read instruction, and a pulse of a write signal WR indicates a write instruction. As for a transfer mode B/W, its low level indicates a byte transfer, and its high level indicates a word transfer. Hereinafter, a case is explained in which the data D0 to D2 having a 3-byte (odd-byte) length are transferred.
First, the data D0 are read from the location 1 of the address AD at a timing t1, and the data D0 are written into the location 101 of the address AD at a timing t2. Then, the data D1 are read from the location 2 of the address AD at a timing t3, and the data D1 are written into the location 102 of the address AD at a timing t4. At last, the data D2 are read from the location 3 of the address AD at a timing t5, and the data D2 are written into the location 103 of the address AD at a timing t6, the data transfer coming to an end.
Word transfers are possible for a transfer of data starting from an even address, but in the case of data starting from an odd address as described above (the location 1), byte transfers are performed for all of the data. Assuming that a set of read and write is one cycle, this data transfer takes three cycles.
FIG. 14 shows another DMA method according to the prior art. An exemplary case of a transfer of data starting from a location 1 (an odd address) and having a 4-byte (even-byte) length is explained here.
First, data D0 are read from a location 1 of an address AD at a timing t1, and the data D0 are written into a location 101 at a timing t2. Then, data D1 are read from a location 2 at a timing t3, and the data D1 are written into a location 102 at a timing t4. Subsequently, data D2 are read from a location 3 at a timing t5, and the data D2 are written into a location 103 at a timing t6. At last, data D3 are read from a location 4 at a timing t7, and the data D3 are written into a location 104 at a timing t8, the data transfer coming to an end.
Since this case is also the transfer of data starting from an odd address (the location 1), byte transfers are performed for all of the data. Assuming that a set of read and write is one cycle, this data transfer takes four cycles.
A data transfer in words only requires half the number of transfers of that in bytes. Data can be transferred more quickly as the number of transfers is reduced, but data starting from an odd address cannot be transferred in words but in bytes.
In addition, data are transferred between devices having different data bus widths to match the data bus having a smaller width. This causes frequent use of the bus, interfering with efficient use of the bus.